A dedicated chip initiative for military aerospace, satellite remote sensing, and strategic visual data processing

Shanghai, China--(Newsfile Corp. - September 4, 2026) - LONXANG / LonXang (Shanghai) Intelligent Technology Development Co., Ltd. today announced the advancement of a dedicated neural image codec chip solution designed for national defense technology, military aerospace, satellite remote sensing, space-ground communications, and major security infrastructure.

Built around LONXANG's fully self-developed M2 neural image codec technology, the proposed solution is intended to address a fundamental challenge in aerospace and defense information systems: how to process, store, transmit, and retrieve increasingly large volumes of high-value visual data under strict constraints on bandwidth, power, storage capacity, and response time.

The M2 software engine has completed product-level integration and is ready to advance into chip tape-out preparation. The dedicated chip is being developed around a proposed 28nm process, marking the next step in the evolution of M2 from a software neural codec engine toward a specialized, system-level visual data processing capability.

Hongliang Mo, inventor of the M2 engine and lead architect of its core architecture, directs the engine's overall design, core codec architecture, and evolution from software implementation toward dedicated chip architecture. "Visual data has become a strategic resource for aerospace missions, remote sensing, command support, and national information infrastructure," Mo said. "Our objective is to transform neural image coding from an isolated software function into a dependable processing layer that can be integrated into satellite payloads, ground stations, defense data centers, edge nodes, and future specialized computing platforms."

From Neural Algorithms to a Dedicated Dataflow Architecture

M2 is an end-to-end neural image coding system. Its technical foundation includes learned analysis and synthesis transforms, hyperprior and context-based probability modeling, quantization, cumulative distribution construction, entropy coding, and independently decodable data encapsulation. These elements form an integrated architecture for the proposed chip rather than a collection of disconnected acceleration blocks.

A dedicated neural codec chip must do more than execute a neural network. It must coordinate neural inference, probability generation, quantization, entropy coding and decoding, on-chip and external memory, DMA transfers, task queues, host interfaces, firmware, drivers, and error handling. It must also preserve bitstream compatibility and provide predictable behavior for long-term data management.

The proposed 28nm architecture is designed as a complete visual dataflow solution. Depending on the final system configuration, it may support sensor-side processing, payload-level data preparation, ground-station ingestion, storage-node acceleration, and high-throughput visual data services. Interface, memory, performance, power, package, and system-integration specifications will be established as the design advances and will be supported by prototype and system testing.

Built for Strategic Visual Data Workloads

In military aerospace and satellite applications, imaging systems must operate with limited communication windows and constrained onboard resources. A codec layer designed for these environments can help organize visual data before transmission, reduce the physical burden of data movement, and support differentiated handling of mission-critical imagery, browsing products, analytical copies, and long-term archives.

Potential application directions include satellite remote-sensing payloads, military aerospace imaging systems, space-ground information links, national geospatial information infrastructure, strategic monitoring systems, aerospace data centers, and high-reliability edge processing nodes. The technology may also be evaluated for secure private deployments where visual data must remain within controlled facilities or mission networks.

The proposed solution is not limited to a single satellite or mission profile. By establishing a reusable codec architecture, M2 is intended to support a broader ecosystem in which the same data-efficiency layer can evolve across software engines, platform accelerators, FPGA prototypes, ASIC implementations, boards, terminals, servers, and specialized aerospace systems.

For organizations responsible for aerospace missions, this approach can strengthen continuity across the visual-data lifecycle. The same architectural principles can support image preparation at the edge, controlled transmission between space and ground, structured storage in secure facilities, and later retrieval for analysis or review. It creates an opportunity to treat visual-data efficiency as a long-term infrastructure capability rather than a one-time payload feature.

Advancing from Software Integration Toward Tape-Out

LONXANG is pursuing a clear product path for the technology. The M2 software engine and its bitstream architecture provide the foundation, while platform integration and hardware prototypes are being used to advance the dataflow, operator mapping, buffering, DMA scheduling, throughput, latency, power, and resource design required for a dedicated chip. These stages will guide subsequent ASIC design, process assessment, verification, and system integration.

The proposed chip is planned around a 28nm process, and LONXANG is advancing its engineering design and tape-out preparation. As a forward-looking technology initiative for national defense and aerospace information infrastructure, its performance, reliability, and deployment capabilities will be established through subsequent chip design, prototype testing, and system validation.

Advancing the Economics of Aerospace Data

As satellite resolution, revisit frequency, and mission data retention continue to increase, the cost of visual data is measured not only by sensor generation, but also by transmission, storage, replication, retrieval, and analysis. A specialized neural codec layer can provide a foundation for reducing unnecessary data movement while preserving the visual information required by downstream users and mission workflows.

LONXANG believes that the next generation of aerospace information infrastructure will require both stronger sensing capabilities and more efficient data foundations. The M2 neural codec chip solution is intended to contribute to that foundation by combining learned image representation, practical bitstream processing, hardware-oriented dataflow, and an architecture designed for long-term integration.

About LONXANG

LONXANG / LonXang (Shanghai) Intelligent Technology Development Co., Ltd. focuses on AI-native visual computing, trusted digital infrastructure, and advanced data-efficiency technologies. Through the M2 ecosystem, the company is developing neural image codec engines, native runtimes, SDK capabilities, platform adaptation, and a phased path toward FPGA, ASIC, and specialized chip integration.

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